1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory using nonvolatile transistors for memory cells, such as an EPROM and an EEPROM.
2. Description of the Related Art
EPROMs and EEPROMs may be enumerated as nonvolatile semiconductor memories using nonvolatile transistors each with the floating gate structure as memory cells. In this type of the nonvolatile semiconductor memory, when a "1" level signal is applied to a word line coupled with the gate of nonvolatile transistor as memory cell, the data programmed in the memory cell is read out onto a bit line coupled with the drain of the transistor, and is applied to a sense amplifier. If the floating gate of the memory cell is in an electron injection state and its threshold voltage V.sub.TH is high, this memory cell is apparently in an off state when the "1" level signal is applied to the word line. At this time, a potential on the bit line remains unchanged and the sense amplifier maintains its initial output state. In another condition that the floating gate of the memory cell is in nonelectron injection state and the threshold voltage V.sub.TH is in low, the memory cell is apparently in an on state when the "1" level signal is applied to the word line. At this time, the bit line is pulled down by the earth potential and the output of the sense amplifier that has been in the initial state is inverted.
Thus, the sense amplifier is operated depending on whether or not electrons have been injected into the floating gate of the memory cell, that is, whether the threshold voltage of the memory cell is high or low, the sense amplifier is operated and check is made as if the programmed data is "1" or "0". Accordingly, as a difference .DELTA.V.sub.TH of the threshold voltages between the memory cell injected with electrons and the memory cell injected with no electron, becomes larger, an operation margin of the sense amplifier increases.
In an initial state of a general EPROM immediately after data is programmed, the threshold voltage of the nonelectron injected cell is approximately 2 V, and that of the electron injected cell is approximately 6 V. Accordingly, the difference .DELTA.V.sub.TH of the threshold voltages between the electron injected cell and the nonelectron injected cell is approximately 4 V, not large. The difference .DELTA.V.sub.TH decreases as the data retaining time increases.
Normally, the EPROM uses a power source voltage of 5 V for the read voltage, i.e., "1" level signal, to be applied to the gate of the memory cell. This voltage of 5 V is closer to the threshold voltage of the electron injected cell rather than a mid potential between the threshold voltage of the electron injected cell and that of the nonelectron injected cell. Therefore, as the data retaining time is longer, the threshold voltage of the electron injected cell drops up to the read voltage of 5 V, and the electron injected cell which should be in an off state, is turned on mistakenly. This makes it difficult to discriminate an on-state memory cell from an off-state memory cell and vice versa. This greatly reduces an operation margin of the EPROM when it is in a read mode.
As described above, in the conventional nonvolatile semiconductor memory, the read voltage applied to the gate of the memory cell is fixed at the power source voltage irrespective of the threshold voltage of the electron injected cell and the nonelectron injected cell. For this reason, the operation margin of the memory cannot be improved in a read mode.